In the fabrication of ultra-large-scale integrated (ULSI) circuits, vertical stacking, or integration, of a plurality of metal wiring circuits, or metal layers, to form a multilevel interconnection has become an efficient way to improve circuit performance and increase the functional complexity of the circuits. One drawback of multilevel interconnection is the loss of topological planarity resulting from various photolithographic and etching processes. To alleviate these problems, the wafer is planarized at various stages in the fabrication process to minimize non-planar topography and thus its adverse effects. Such planarization is typically implemented in the dielectric layers.
More recently, chemical-mechanical polishing (CMP) processes have become very well received to planarize the wafer surface in preparation for further device fabrication. The CMP process mainly involves holding a semiconductor wafer against a rotating polishing pad surface wetted by a polishing slurry, which typically comprises an acidic or basic etching solution in combination with alumina or silica particles. On the one hand, the liquid portion of the slurry chemically removes, loosens, or modifies the composition of the material on the wafer which is to be removed. On the other hand, the particle portion of the slurry, in combination of the rotating polishing pad, physically removes the chemical modified material from the wafer. Thus, the name chemical-mechanical polishing was obtained.
CMP processes have been used to polish surfaces that are made of silicon oxide, silicon nitride, aluminum, copper, tungsten, etc. At the present time, the mechanical force distribution on the CMP polishing head is adjusted on a post-priori manner, i.e., by examining the CMP-polished surface and then adjust the CMP polishing head on a trial-and-error, or, at best, an empirical, manner. There is no available technique that exists today that will allow the semiconductor manufacturer to measure, obtain a feedback, and then adjust and control the distribution of the mechanical force exerted by the CMP polishing head on the wafer surface.
What makes the adjustment process difficult is that there exist many other factors that can also affect the result of a CMP process. These include the overall pressure, polishing temperature, slurry composition, wafer material, circuit pattern, the type of sacrificial material used for planarization, etc. By only examining the polished surface, it is essentially impossible to isolate the effect of one factor from the others. As a result, the CMP process is often described as an "art" and not considered as a "science". In other words, the CMP processes are typically adjusted based on empirical experience and not probed in a scientific manner.
With the significant advancement of the semiconductor fabrication process, it is important to reduce such empiricism and elevate our understanding of the CMP process as much as possible. It is particularly desirable to develop a method which will allow semiconductor manufacturers to understand the pressure distribution on the CMP head, so as to allow proper adjustment to be made so as to optimize and improve the CMP process.